Qualcomm Inc. and Google LLC today announced that they’re teaming up to develop RISC-V processors for wearable devices.

The initiative comes less than a month after the search giant hosted the latest installment of its Made by Google product event. At the event, the Alphabet Inc. unit debuted two new additions to its Pixel line of Android smartphones. It also introduced the latest iteration of its Pixel Watch 2 smartwatch. 

Google has disclosed that the Pixel Watch 2 runs on Qualcomm’s Snapdragon W5 Gen 1 Wearable processor. It’s a system-on-chip, or SOC, a chip that combines multiple computing modules in a single package. There’s a graphics processing unit, a modem capable of establishing 4G connections and multiple digital signal processors.

The bulk of the chip’s processing power comes from a quad-core central processing unit with a 1.7 GHz clock frequency. According to Qualcomm, the CPU is made using a four-nanometer manufacturing process. The CPU’s four cores are based on Arm Holdings plc’s A53 core design, which is optimized for power efficiency rather than performance. 

The Snapdragon W5 Gen 1 Wearable is part of a Qualcomm chip series called Snapdragon Wear. As part of their newly announced partnership, the chipmaker and Google will develop new Snapdragon Wear processors in which the Arm CPU cores used today will be substituted with RISC-V silicon. Those upcoming processors will be optimized to power wearable devices such as smartwatches that run Google’s Wear OS operating system. 

Wear OS ships with, among other products, the Pixel Watch 2 that the search giant detailed today at its Made by Google event. As a result, it’s possible the RISC-V Snapdragon Wear chips the company is developing with Qualcomm could potentially find their way into future Pixel Watch iterations. 

Qualcomm hinted that its RISC-V silicon will also be available for other device makers besides Google. According to the company, one of its goals for the upcoming chips is to “help reduce time to market for OEMs when launching smartwatches.”

Google and Qualcomm said another priority of their partnership will be to ensure “applications and a robust software ecosystem” will be available for RISC-V wearables. Currently, relatively few consumer apps can run on RISC-V devices, which may limit their appeal. Google and Qualcomm said that they have already started working on expanding software support for the technology.

“Our Snapdragon Wear platform innovations will help the Wear OS ecosystem rapidly evolve and streamline new device launches,” said Dino Bekis, the vice president and general of Qualcomm’s wearables and mixed signal solutions business.

Royalty-free chips 

Originally developed at the University of California at Berkeley in 2010, RISC-V is an open-source reduced instruction set architecture. A processor’s instruction set architecture is the language in which it expresses computations. The individual “words” that make up this language are simple operations like addition, subtraction and multiplication.

CPUs string together a large number of such words, or instructions, to perform complex tasks like launching applications and downloading updates. To simplify processing, instruction set architectures also provide other technical building blocks besides the instructions themselves. Those other building blocks ease auxiliary tasks such as managing the memory in which a processor stores its data.

Most wearables, including the new Pixel Watch 2 that Google debuted this morning, use Arm’s namesake instruction set architecture. Arm charges licensing fees from companies that use its architecture. RISC-V, in contrast, is free, which is one of the main reasons it’s drawing interest from industry players such as Google and Qualcomm.

Switching from Arm to RISC-V can theoretically enable a chipmaker to reduce its costs. Moreover, the fact that RISC-V is open-source simplifies licensing. Instruction set architectures distributed under a commercial license often have usage limitations. 

The downside of RISC-V is that, although it’s not a new technology, industry adoption is at a fairly nascent stage. Relatively few chip engineers have experience building RISC-V processors. Additionally, the number of development tools and other software products that are compatible with the architecture is limited.

Over the past few quarters, Qualcomm and other industry players have taken steps to address those challenges.

This past August, Qualcomm and four fellow chipmakers launched a joint venture to broaden the adoption of RISC-V processors. The Germany-based venture will initially focus on increasing RISC-V usage in the auto sector. Qualcomm has a business unit dedicated to making chips for smart cars and autonomous vehicles. 

Earlier, an industry consortium backed by Qualcomm and Google launched a RISC-V initiative called RISE. The initiative aims to increase the number of software products that can run on RISC-V chips. The consortium’s initial focus is to add compatibility with foundational software technologies such as Linux distributions, programming languages and compiler tools. 

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